1. Field of the Invention
This invention is related to the field of processors and, more particularly, to capturing status/control register updates in processors.
2. Description of the Related Art
Processors are designed to execute instructions defined in an instruction set architecture. There are a variety of instruction set architectures in use (e.g. the PowerPC™ architecture defined by IBM, the MIPS™ architecture defined by MIPS, the ARM™ architecture defined by ARM, the SPARC™ architecture defined by Sun Microsystems, the IA-32 (or x86) architecture defined by Intel, etc.). Typically, the instruction set architecture assumes a sequential execution model for defining the instructions (in which each instruction completes execution in-order, non-speculatively).
To increase performance, many processors implement speculative execution in which a given instruction may be executed speculatively (that is, prior to ensuring that the instruction is actually to be executed according to the sequential execution model). For example, instructions may be executed out of order with respect to the program order of the instructions. Instructions may be executed that are dependent on a prediction, such as a branch prediction. If a preceding instruction experiences an exception or misprediction, the speculatively executed instructions are not, in fact, executed and the results of their speculative execution must be discarded.
One method for supporting speculative execution includes the use of speculative registers to store the speculatively-generated results of instruction execution. If the speculative execution is correct, the speculatively-generated results are moved from the speculative registers to architected registers defined in the instruction set architecture. If the speculative execution is not correct, the speculatively-generated results are not moved and thus the speculative results are effectively discarded.
In some cases, instructions may generate updates for other registers besides the destination register that stores the result. For example, status/control registers may be defined that store exception bits indicating exceptions that occur during instruction execution. The speculative registers may be defined to store the contents of the status/control register (as updated in response to the instruction) in addition to the result data, or a different speculative register may be assigned to store the contents. Unfortunately, the amount of space needed to store both the result data and the data to update the status/control register may be large, and may increase the size of the storage needed to implement the speculative registers.